Digital Low Power Base Band Processor for RFID Tags

Two’s complement multipliers are important for a wide range of applications. In this paper, we present a technique to reduce by one row the maximum height of the partial product array generated by a radix-4 Modified Booth Encoded multiplier, without any increase in the delay of the partial product generation stage. This reduction may allow for a faster compression of the partial product array and regular layouts. This technique is of particular interest in all multiplier designs, but especially in short bit-width two’s complement multipliers for high-performance embedded cores. The proposed method is general and can be extended to higher radix encodings, as well as to any size square and m_ n rectangular multipliers. We evaluated the proposed approach by comparison with some other possible solutions; the results based on a rough theoretical analysis and on logic synthesis showed its efficiency in terms of both area and delay.

  • Project Category : Non -IEEE Projects
  • Project Year : 2013-2014
  • Department
  • B.E(Electronics and Communication), B.Tech, M.E(VLSI), M.Tech,
  • Domain
  • VLSI,
  • Technology
  • RTL-Verilog/VHDL,
  • Avilable city
  • Hyderabad,

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