Variation-Aware Variable Latency Design

Abstract: The traditional paradigm of optimizing a chip for the worst case delay can lead to significant inefficiencies. Variable latency units (VLUs) allow for improved throughput by allowing one clock cycle for some computations, and two clock cycles for others, using hold logic to differentiate between the two cases. However, they may experience significant throughput losses due to the effects of process variations. In the existing system, they developed a combined presilicon-postsilicon technique for variation aware VLU design that ensures high throughputs across all manufactured chips. They achieved this by identifying path clusters at the presilicon stage, such that each element of a path cluster is likely to be similarly critical in a manufactured part. They use sensors to determine which path clusters is critical at the postsilicon stage and then activate the appropriate hold logics. Practically, for a small number of path clusters, significant improvements in throughput are achievable. On a set of 32-nm PTM-based ISCAS89 circuits, this scheme offers 15.1% throughput enhancements with only 3.3% area overhead. Existing system: In the existing system, they developed a combined presilicon-postsilicon technique for variation aware VLU design that ensures high throughputs across all manufactured chips. They achieved this by identifying path clusters at the presilicon stage, such that each element of a path cluster is likely to be similarly critical in a manufactured part. They use sensors to determine which path clusters is critical at the postsilicon stage and then activate the appropriate hold logics. For a small number of path clusters, significant improvements in throughput are achievable. On a set of 32-nm PTM-based ISCAS89 circuits, this scheme offers 15.1% throughput enhancements with only 3.3% area overhead. Disadvantages: • Delay reduction is not taken place. • The power is reduced to some extent. Proposed system: In the proposed system, we are implementing a design to reduce the critical path of the circuit. Also we are detecting the latency that where it occurs, and reducing the fault that exists because of the latency problem. We are designing a module that achieve throughput increase thus reducing the critical path. Advantages: • Measures taken to increase throughput. • Reduced number of faults. Software requirements: Design Environment: XILINX ISE Language: VHDL Simulation: MODELSIM / XILINX ISE Simulator Hardware requirements: XILINX SPARTAN Development Board, CPLD Device: XC3S500E, XC9572XL

  • Project Category : IEEE Projects
  • Project Year : 2013-2014
  • Department
  • B.E(Electrical and Electronics Engg), B.E(Electronics and Communication), M.E(VLSI), M.Tech,
  • Domain
  • Image Processing, VLSI,
  • Technology
  • Avilable city
  • Bangalore, Chennai, Coimbatore, Delhi, Hyderabad, Madurai, Pondicherry, Salem, Thanjavur, Trichy,

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