Ultra-High Throughput Low-Power Packet Classification

Network processors are key components used to process packets as they pass through a network, carrying out tasks such as packet fragmentation and reassembly, encryption, forwarding, and classification. The process of categorizing packets into “flows” in an Internet router is called packet classification. Packet classification is a difficult task due to the fact that all packets must be processed at wire speed and rulesets can contain tens of thousands of rules. In the existing system, they designed a hardware accelerator that can classify up to 433 million packets per second when using rulesets containing tens of thousands of rules with a peak power consumption of only 9.03 W when using a Stratix III field programmable gate array (FPGA). The hardware accelerator used a modified version of the HyperCuts packet classification algorithm, with a new pre-cutting process used to reduce the amount of memory needed to save the search structure for large rulesets so that it is small enough to fit in the on-chip memory of an FPGA. The modified algorithm also removes the need for floating point division to be performed when classifying a packet, allowing higher clock speeds and thus obtaining higher throughputs.

  • Project Category : IEEE Projects
  • Project Year : 2014-2015
  • Department
  • B.E(Electrical and Electronics Engg), B.E(Electronics and Communication), M.E(VLSI),
  • Domain
  • VLSI,
  • Technology
  • FPGA Implementation, RTL-Verilog/VHDL,
  • Avilable city
  • Bangalore, Chennai, Coimbatore, Hyderabad, Madurai, Salem, Trichy,

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