Pulsed-Latch Utilization for Clock-Tree Power Optimization

Power consumption has become a crucial issue in high-performance circuits. Hence an approach to reduce the power consumption in modern circuits is produced. The most existing power-aware clock-tree minimization algorithms optimize power on the basis of flip-flops alone, which may result in limited power savings. In the existing design, to achieve a power and timing tradeoff, the pulsed-latch utilization in a clock tree for further power savings is introduced. A migration approach to efficiently construct a clock tree with both pulsed-latches and flip-flops is given. The existing method is based on minimum-cost maximum-flow formulation to globally determine the tree topology, which maintains load balance and considers the wirelength between pulse generators and pulsed latches. Experimental results indicate that the existing migration approach can improve the power consumption by 12% and 13% with 7% and 70% skew improvements on average compared with the most recent paper on the industrial circuits and ISPD-2010 benchmarks, respectively.

  • Project Category : IEEE Projects
  • Project Year : 2014-2015
  • Department
  • B.E(Electrical and Electronics Engg), B.E(Electronics and Communication), M.E(VLSI),
  • Domain
  • Embedded system, VLSI,
  • Technology
  • FPGA Implementation, RTL-Verilog/VHDL,
  • Avilable city
  • Bangalore, Chennai, Coimbatore, Hyderabad, Madurai, Salem, Trichy,

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