On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions

Modern on-chip communication protocols support advanced transactions to improve communication efficiency. Out-of-order transactions play an important role, but a deadlock situation may occur if these transactions are not properly manipulated. In the existing system, they addressed the deadlock problem in an on-chip bus system supporting out-of-order transactions. They presented a graphic model that can well represent the status of a bus system and showed that a cycle exists in the graph if and only if the bus system is in an unsafe state that may lead to a bus deadlock. Based on this model, they proposed a novel bus design technique that can efficiently resolve the bus deadlock problem. Experimental results showed that buses with the existing technique can be up to 3.3 times faster than those with the previously available techniques.

  • Project Category : IEEE Projects
  • Project Year : 2014-2015
  • Department
  • B.E(Electrical and Electronics Engg), B.E(Electronics and Communication), M.E(VLSI), M.SC(CS),
  • Domain
  • Embedded system, VLSI,
  • Technology
  • FPGA Implementation, RTL-Verilog/VHDL,
  • Avilable city
  • Bangalore, Chennai, Coimbatore, Hyderabad, Madurai, Salem, Trichy,

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