This paper presents an area-time-efficient systolic structure for multiplication over GF (2m) based on irreducible all-one polynomial (AOP). We have used a novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay. It is further shown that the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input operand, and they can share the same input operand registers. From the field-programmable gate array synthesis results we find that the proposed design provides extensively less area-delay and Power-delay complexities over the best of the existing designs.

  • Project Category : IEEE Projects
  • Project Year : 2013-2014
  • Department
  • B.E(Electronics and Communication), B.Tech, M.E(VLSI), M.Tech,
  • Domain
  • VLSI,
  • Technology
  • RTL-Verilog/VHDL,
  • Avilable city
  • Hyderabad,

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