Incremental Trace-Buffer Insertion for FPGA Debug

As integrated circuits encapsulate more functionality and complexity, verifying that these devices operate correctly under all scenarios is an increasingly difficult task. Field-programmable gate-array (FPGA)-based prototypes achieve significantly higher clock speeds but lack of On-chip observability. So trace buffer insertion to record the limited set of internal signals are handled over here, but modifying this trace configuration often requires the entire circuit to be recompiled. In the existing system, the original circuit mapping is fully preserved and incremental techniques are used to eliminate the need for a full recompilation, thereby accelerating the debugging process. By exploiting two opportunities available during trace-insertion: the ability to connect from any point of a signal to any trace-pin, and the internal symmetry of the FPGA architecture, we find that incremental trace-insertion can be 98 times faster than a full recompilation, return a routing solution with a shorter wirelength, and have a negligible effect on the critical-path delay of the original circuit when reclaiming 75% of the leftover memory capacity for tracing.

  • Project Category : IEEE Projects
  • Project Year : 2014-2015
  • Department
  • B.E(Electrical and Electronics Engg), B.E(Electronics and Communication), M.E(VLSI),
  • Domain
  • VLSI,
  • Technology
  • FPGA Implementation, RTL-Verilog/VHDL,
  • Avilable city
  • Bangalore, Chennai, Coimbatore, Hyderabad, Madurai, Salem, Trichy,

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