Implementation of Delay Test for Diagnosis of Power Switches

Abstract: Power gating is a low-power design technique to reduce leakage power. It has gained popularity in sub-100-nm CMOS designs, where leakage power is a major contributor to the overall power consumption. Power switches are used as a part of the power gating technique to reduce the leakage power of a design. Thus, the diagnosing of power switches is presented over here. In the existing system, the design-for-test solution for efficient testing of power switches in the presence of process, voltage, and temperature variation is presented. It divides power switches into segments such that any faulty power switch is detectable, thereby achieving high diagnosis accuracy. The diagnosis method is validated through SPICE simulation using a number of ISCAS benchmarks synthesized with a 90-nm gate library. Simulation results show that, when considering the influence of process variation, the worst case loss of accuracy is less than 4.5%; it is less than 12% when considering VT variations. Proposed system: In the proposed system, the power switches are tested by designing a module called random testing. We are also doing this test repeatedly to accurately diagnose the faults that where it is and the number of faults. Also we are designing a framed testing module. All these implementations are done in Modelsim only. Advantages: • Accurate fault diagnosis is achieved, because of using random testing. • Faster testing time and good efficiency.

  • Project Category : IEEE Projects
  • Project Year : 2013-2014
  • Department
  • B.E(Electrical and Electronics Engg), B.E(Electronics and Communication), M.E(APPLIED ELECTRONICS), M.E(VLSI), M.Tech,
  • Domain
  • Bluetooth / GSM Applications, Image Processing, MATLAB Projects, VLSI,
  • Technology
  • Avilable city
  • Bangalore, Chennai, Coimbatore, Delhi, Hyderabad, Madurai, Pondicherry, Salem, Thanjavur, Trichy,

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