IEEE 2016 - 2017 VLSI RF Power Gating: A Low-Power Technique for Adaptive Radios

In this paper, we propose a low-power technique,called RF power gating, which consists in varying the active timeratio (ATR) of the RF front end at a symbol time scale. Thistechnique is especially well suited to adapt the power consumption of the receiver to the performance needs without changingits architecture. The effect of this technique on the bit errorrate (BER) performances is studied for a basic estimator in thespecific case of minimum-shift keying signaling. A system-levelenergy model is also derived and discussed to estimate preciselythe power reduction based on the characteristics and the powerconsumption of each block. This model allows highlighting thedifferent contributors of the power reduction. The BER resultsand the energy model are finally merged to determine the bestATR meeting the design constraints. Applying this techniqueto the IEEE 802.15.4 standard, this paper shows that an ATRof 20% is a good tradeoff to meet the packet error rate constraintwhile maximizing the energy reduction ratio. Using typical blockpower consumptions, an energy reduction ratio around 20% canbe reached. Even better energy reduction ratios (?60%) are alsoachievable when most of the blocks are power-gated.The proposed architecture of this paper analysis the logic size, area and power consumption using Xilinx 14.2.

  • Project Category : IEEE Projects
  • Project Year : 2016-2017
  • Department
  • Any degree, B.E (civil), B.E(Aeronautical Engineering), B.E(Automobile), B.E(Bio Medical Engg), B.E(Computer Science) , B.E(Electrical and Electronics Engg), B.E(Electronics and Communication), B.E(Information Technology), B.E(Instrumentation Control and Engg), B.E(Mechanincal Engineering), B.E(Mechtronics), B.SC(CS), B.SC(IT), B.Tech, BCA, M.E(APPLIED ELECTRONICS), M.E(Computer Science), M.E(CONTROL SYSTEM), M.E(Mechanical Engineering), M.E(POWER ELECTRONICS), M.E(SOFTWATE ENGG), M.E(VLSI), M.SC(CS&M), M.SC(CS), M.SC(IT&M), M.SC(IT), M.SC(SOFTWARE ENGG), M.Tech, MCA,
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  • Technology
  • ASIC- Schematic/Layout, ASP.Net, C, C#.Net, C++, Civil, Communication, .Net, FPGA Implementation, Image processing, J2EE, J2ME, Java, matlab, NS2, PHP, PIC/Arduino/ARM, PLC, Raspberry Pi, RTL-Verilog/VHDL, SCADA, Signal processing, tanner, UCOSII, VB.Net, VC++, visual basic 6.0,
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  • Ahmedabad, Bangalore, Chennai, Coimbatore, Davangere, Delhi, Dharmapuri, Ernakulam, Hyderabad, Kolkata, Kozhikode, Madurai, Mumbai, Pondicherry, Pune, Salem, Thanjavur, Tirunelveli, Trichy, Vellore,


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