Design of Gated-Latch Utilization Technique for Clock-Tree Power Optimization system

Abstract: Clock gating is a predominant technique used for power saving. Data-driven clock gating aims to disable a large amount of redundant clock pulses. The Flip-Flop (FF) grouping in Data-Driven Clock Gating is implemented here, so that they share a common clock enabling signal. In the existing system, a practical solution based on the toggling activity correlations of FFs and their physical position proximity constraints in the layout is proposed. The data-driven clock gating is integrated into an Electronic Design Automation (EDA) commercial backend design flow, achieving total power reduction of 15%–20% for various types of large-scale state-of-the-art industrial and academic designs in 40 and 65 nanometer process technologies. These savings are achieved on top of the savings obtained by clock gating synthesis performed by commercial EDA tools, and gating manually inserted into the register transfer level design

  • Project Category : IEEE Projects
  • Project Year : 2014-2015
  • Department
  • B.E(Electrical and Electronics Engg), B.E(Electronics and Communication), M.E(VLSI), M.Tech,
  • Domain
  • GPRS/EMBEDDED Networking Based Projects, MATLAB Projects, VLSI,
  • Technology
  • FPGA Implementation, RTL-Verilog/VHDL,
  • Avilable city
  • Bangalore, Chennai, Coimbatore, Delhi, Hyderabad, Madurai, Pondicherry, Salem, Thanjavur, Trichy,

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