A parallel radix-sort-based VLSI architecture for ?nding the ?rst W maximum/minimum values

VLSI architectures for ?nding the ?rst W (W > 2) maximum (or minimum) values are required in the implementation of several applications such as non-binary LDPC decoders, K-best MIMO detectors and turbo product codes. In this work a parallel radix-sort-based VLSI architecture for ?nding the ?rst W maximum (or minimum) values is proposed. The described architecture, named Bit-Wise-And (BWA) architecture, relies on analyzing input data from the most signi?cant bit to the least signi?cant one, with very simple logic circuits. One key feature in the BWA architecture is its high level of scalability which enables the adoption of this solution in a large spectrum of applications, corresponding to large ranges for both W and the size of the input data set. Experimental results, achieved implementing the proposed architecture on a high speed 90 nm CMOS standard cell technology, show that BWA architecture requires signi?cantly less area than other solutions available in the literature, i.e. less than or about 50% in all the considered cases. Moreover, the BWA architecture exhibits the lowest area-delay product among almost all considered cases.

  • Project Category : IEEE Projects
  • Project Year : 2014-2015
  • Department
  • B.E(Electronics and Communication), B.Tech, M.E(VLSI), M.Tech,
  • Domain
  • VLSI,
  • Technology
  • RTL-Verilog/VHDL,
  • Avilable city
  • Hyderabad,

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