A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

Abstract—Due to current technology scaling tre nds such as shrinking feature sizes and decreasing supply voltages, circuit reliability is becoming more susceptible to radiation-induced transient faults (soft errors). Soft er rors, which have been a great concern in memories, are now a main factor in reliability degradation of logic circuits as well. In this paper, we present a systematic and integrated methodology for circu it robustness to soft errors. The proposed soft error rate (SER) reduction framework, based on redundancy addition and removal (RAR), aims at eliminating those gates with large contributio n to the overall SER. Several metrics and constraints are introduced to guide the RAR-based approach toward SER reduction. Furthermore, we integrate a resizing strategy into our fr amework, as post-RAR additive SER optimization. The strategy can identify most critical gates to be upsized and thereby, minimize area and power overheads while maintaining a high level of soft error robustness. Experimental results show that the proposed RAR-based framework can achieve up to 70% reduction in output failure probability. On average, about 23% SER reduction i sobtainedwithlessthan4%area overhead.

  • Project Category : IEEE Projects
  • Project Year : 2013-2014
  • Department
  • B.E(Electronics and Communication), B.Tech, M.E(VLSI), M.Tech,
  • Domain
  • VLSI,
  • Technology
  • RTL-Verilog/VHDL,
  • Avilable city
  • Hyderabad,

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