A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks

Abstract:- Energy constrained wireless communication applications realization is done here, to facilitate low transmission energy consumption, reduce the overall energy consumption; lookup table-log-BCJR (LUT-Log-BCJR) architectures having low processing energy consumption are required. In this existing design, we decompose the LUT-Log-BCJR architecture into its most fundamental add compare select (ACS) operations and perform them using a novel low-complexity ACS unit. We demonstrate that our architecture employs an order of magnitude fewer gates than the most recent LUT-Log-BCJR architectures, facilitating a 71% energy consumption reduction. Compared to state-of-the-art maximum logarithmic Bahl-Cocke-Jelinek-Raviv implementations, our approach facilitates a 10% reduction in the overall energy consumption at ranges above 58 m.

  • Project Category : IEEE Projects
  • Project Year : 2013-2014
  • Department
  • B.E(Computer Science) , B.E(Electrical and Electronics Engg), B.E(Electronics and Communication), B.E(Information Technology), B.E(Instrumentation Control and Engg), B.E(Mechtronics),
  • Domain
  • Digital Signal Processing, Embedded Electrical, Embedded system, GPRS/EMBEDDED Networking Based Projects, GPS Based Embedded Projects, Image Processing, MEMS Based Embedded Projects, RF / RFID Projects, Robotics, RTOS, VLSI,
  • Technology
  • FPGA Implementation, RTL-Verilog/VHDL,
  • Avilable city
  • Bangalore, Chennai, Coimbatore, Delhi, Hyderabad, Madurai, Pondicherry, Salem, Thanjavur, Trichy,

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